1. Field of the Invention
The present invention relates generally to nonlinearity in analog-to-digital converters with particular relation to pipelined analog-to-digital converters.
2. Description of the Related Art
Analog-to-digital converters (ADCs) convert analog input signals to digital output signals with a resolution that determines the number of bits in the converted signals. For example, FIG. 1 shows an exemplary pipelined ADC 20 which includes a sampler 22 that provides samples of an analog input signal Sin and N cascaded converter stages 24 that partition the conversion of these samples to a digital code.
Each pipelined stage converts a respective analog signal to that stage""s predetermined number m of digital bits and passes an amplified residue signal to a succeeding converter stage. As the succeeding converter stage converts its received residue signal in a similar manner, the preceding stage is converting a succeeding analog input signal. All converter stages, therefore, are simultaneously converting succeeding analog input signals to their respective digital bits with final converted words issuing at the same rate as the sampling rate of input analog signals.
Broken lines 26 in FIG. 1 indicate that the ith converter stage, for example, comprises an mi-bit ADC 30 which provides digital bits Di and also comprises an mi-bit digital-to-analog (DAC) 32 that converts these bits to an analog signal which is subtracted in a summer 34 from this stage""s respective analog input to form an analog residue Ri that is amplified in a respective amplifier 36 with a respective gain Gi and passed to a successive converter stage.
Generally, one or more redundant bits are generated and a control and correction logic 38 includes circuits (e.g., full adders) that use the bits of succeeding stages to correct preceding-stage errors that result from various degrading effects (e.g., offset and/or gain errors) and also includes circuits (e.g., shift registers) that time-align the corresponding digital bits
Especially useful embodiments of pipelined ADCs are formed with switched-capacitor structures and the high-speed, high-resolution conversion of these ADCs is used in a large number of modern electronic systems (e.g., scanners, camcorders, communications modems, medical image processors and high-definition television). It has been found, however, that various error sources (e.g., nonlinear sampler, capacitor mismatch, finite and/or nonlinear amplifier gain) degrade their conversion linearity. Accordingly, a number of calibration structures and methods have been developed to reduce this degradation.
Even with careful design and with currently-available calibration techniques, however, ADCs (and pipelined ADCs in particular) are produced in which the differential nonlinearity (DNL) is sufficiently reduced but the integral nonlinearity (INL) is excessive which causes the converter""s spurious-free dynamic range (SFDR) to be less than satisfactory.
The present invention is directed to structures and methods that reduce an initial converter nonlinearity of ADCs. These goals are realized by introducing an inverse nonlinearity into the converter""s response that is substantially the inverse of the initial converter nonlinearity.
In a method embodiment, most-significant bits of the digital code are initially selected that define sufficient most-significant code words to designate respective segments of an inverse nonlinearity that is substantially the inverse of the converter nonlinearity. Subsequently, the remaining least-significant bits of the digital code are adjusted, in respective response to the most-significant code words, to sufficiently modify the conversion gain to insert the inverse nonlinearity into the converter response. The most-significant bits and least-significant bits respectively correspond to upstream converter stages and remaining downstream converter stages in pipelined embodiments of the invention.